Recently, high performance has been required for semiconductor devices, and the semiconductor devices have recently been advanced in high integration. Under such a situation, in a case where the semiconductor devices are manufactured by arranging a plurality of highly integrated semiconductor devices in a horizontal plane and connecting the semiconductor devices with wiring, it is concerned that the wiring length is increased and thus, the wiring resistance and the wiring delay are increased.
Accordingly, a three-dimensional (3D) integration technique for three-dimensionally stacking semiconductor devices has been proposed. In the 3D integration technique, a plurality of electrodes so-called through silicon vias (TSVs) having a minute diameter of, for example, 100 μm or less, are formed through a semiconductor wafer (hereinafter, referred to as a “wafer”) which is thinned by polishing its rear surface and has a plurality of electronic circuits formed on its front surface. And, the vertically stacked wafers are electrically connected to each other through the through silicon vias.
Thus, when a through silicon via is formed in a through-hole, a plating metal is embedded in the through-hole by a plating method such as, for example, electrolytic plating. The electrolytic plating method is implemented in a plating apparatus described in, for example, Patent Document 1. The plating apparatus includes a plating bath that stores a plating liquid. The inside of the plating bath is partitioned by a regulation plate. An anode is arranged in one partitioned section, and a wafer is immersed in the other section so that a potential distribution between the anode and the wafer is adjusted by the regulation plate. After the wafer is immersed in the plating liquid within the plating bath, the anode is set to a positive pole and the wafer is set to a negative pole to apply voltage so that a current flows between the anode and the wafer. By the current, metal ions in the plating liquid are caused to migrate to the wafer side, and the metal ions are precipitated as a plating metal on the wafer side, so that the plating metal is embedded inside the through-hole.